A thorough study of APA102 is on Tim’s blog. I’m just rehashing his findings and the spec sheet here for my own purpose.
APA102C spec sheet:
- Max clock is 800 kHz to 1.2 MHz
- A frame is controlled by one uint32_t set to Zero (START_FRAME) and one set to MaxInt (END_FRAME):
0x0000.0000 LED1 LED2 … LEDn 0xFFFF.FFFF
- A LED value is a uint32_t, with the first byte encoding 3 most significant bits set to 111, and a 5-bit brightness (0..31).
111bbbbb RRRRRRRR GGGGGGGG BBBBBBBB
- You can’t have a white max brightness LED display. Indeed the first byte would be 11111111 with R,G,B all set to 0xFFFF. That means the pixel would be 0xFFFF.FFFF, the same signature as the END FRAME. That’s very odd, until you read Tim’s blog that explains its use: It doesn’t matter.
- The brightness setting seems to be implemented as a 580Hz PWM, that is noticeable when the brightness is set to 30 or lower, while the RGB settings are PWM’d at 19.2kHz.
=> Note to notice discrepancies between LED setting and actual display, we’d have to refresh the LED faster than 50 micro seconds, or with a clock of less than 1.5 micro seconds (614kHz), turning the LED on and off immediately. In that case it is possible the LED does not have time to light up.
- SPI clocks of up to 10MHz have been tested. No upper limit was reported.
- Tim shows clock latch is when clock goes LOW to HIGH. CKout passed to the next LEDs is inverted, and SDO is set on CKin latch. That allows the next LED to latch SDO when it is stable.
=> From this I infer CK should be a 50% duty cycle as much as possible to maximize stability of the LED strip. However the circuits support over 10MHz.
- The START_FRAME with 0x0000.0000 tells a LED there’s no data to read. The first bit to 1 means read the data and store it as the LED value. That information is not pushed to SDO which stays at zero that whole time. Once the LED data is used, all extra data is passed on to SDO. Hence the LED strip is refreshed from the closest to the most remote LED.
- The END_FRAME is only used to push CK for the last pixel. The number of bits of that frame must be at least 1/2 the number of pixels driven. It can contain 1’s or 0’s but not both.